For example, in the case of power amplification of radio-frequency signals such as CDMA (Code Division Multiple Access) signals or multi-carrier signals, reduction of power consumption is achieved by adding a distortion compensation function to a common amplifier and widening the operating range of the common amplifier to an area near a saturation range. The method of distortion compensation includes a feed forward distortion compensation approach or a pre-distortion distortion compensation approach. However, the reduction of power consumption only with the distortion compensation is already near the limit. Therefore, a Doherty amplifier nowadays attracts attention as a high-efficiency amplifier.
FIG. 8 illustrates an example of configuration of the Doherty amplifier.
A signal entering through an input terminal A21 is distributed by a distributor 41.
A part of the distributed signal is supplied to a carrier amplifier 42. The carrier amplifier 42 includes an amplifying element 52, an input matching circuit 51 adapted to achieve matching to an input side of the amplifying element 52 and an output matching circuit 53 adapted to achieve matching to an output side of the amplifying element 52. Impedance conversion is applied to an output from the carrier amplifier 42 by a λ/4 transformer 57.
The other part of the distributed signal is delayed in phase by 90° by a phase shifter 43 and is supplied to a peak amplifier 44. The peak amplifier 44 includes an input matching circuit 54, an amplifying element 55 and an output matching circuit 56 like the carrier amplifier 42.
An output from the λ/4 transformer 57 and an output from the peak amplifier 44 are combined at a node (combining point) 58. The combined signal is applied with the impedance conversion by a λ/4 transformer 46 for achieving matching to Z0, which is an output load 47.
An output from the λ/4 transformer 46 is connected to the output load 47 via an output terminal A22.
A combination of the λ/4 transformer 57 and the node 58 is referred to as Doherty composition 45.
The carrier amplifier 42 and the peak amplifier 44 are different such that the amplifying element 52 of the carrier amplifier 42 is biased to Class AB and the amplifying element 55 of the peak amplifier 44 is biased to Class B or Class C. Therefore, the amplifying element 52 of the carrier amplifier 42 operates independently to an input level at which the amplifying element 55 of the peak amplifier 44 operates and, when the amplifying element 52 of the carrier amplifier 42 reaches the saturation range, that is, when linearity of the amplifying element 52 starts to be turbulent, the amplifying element 55 of the peak amplifier 44 starts to operate to supply the output of the amplifying element 55 to a load so as to drive the load together with the amplifying element 52 of the carrier amplifier 42. Load resistance of the output matching circuit 53 of the carrier amplifier 42 at this moment moves from a high level to a low level. However, since the amplifying element 52 is in the saturation range, the high-efficiency is achieved.
When the input level from the input terminal A21 is further increased, the amplifying element 55 of the peak amplifier 44 also starts to be saturated. However, since both the amplifying elements 52 and 55 are saturated, high-efficiency is also achieved.
FIG. 9 shows an example of theoretical collector efficiency or drain efficiency relating to the Doherty amplifier shown in FIG. 8. In a graph in FIG. 9, the lateral axis represents the back-off (dB) and the vertical axis represents the efficiency (%).
Assuming that the minimum input level to the input terminal A21 at which both the amplifying elements 52 and 55 are saturated, that is, a compression point, to be 0 dB, the back-off here is a numerical value showing an excess of the input level with respect to the compression point.
In this example, the term “collector efficiency” means a ratio of radio-frequency output power which can be gained from a collector with respect to a product of a voltage (direct current) applied to the collector from a power source and an electric current (direct current) supplied from the power source. The drain efficiency has also a similar signification.
The graph in FIG. 9 shows an example of efficiency of a general Class B amplifier (broken line), and an example of efficiency of a simple model of the Doherty amplifier (solid line). A section in which the back-off is 6 dB or higher is designated as Section A, a section in which the back-off is in a range from 0 dB to 6 dB is designated as Section B, and a section in which the back-off is lower than 0 dB is designated as Section C.
Basically, when the input level is in Section A, only the carrier amplifier 42 operates. The carrier amplifier 42 starts to be saturated in the area where the back-off reaches 6 dB, and the efficiency reaches a point near the maximum efficiency of the Class B amplifier. The output of the carrier amplifier 42 at this moment is about (P0/4), where the maximum output of the Doherty amplifier is P0.
In Section B in which the back-off is 6 dB or lower, the output of the carrier amplifier 42 increases from about (P0/4) to (P0/2) as the input level increases, and the output of the peak amplifier 44 increases from about 0 to (P0/2). The sum of the output power from the carrier amplifier 42 and the output power from the peak amplifier 44 here is proportional to the input power to the input terminal A21 at the same constant of proportionality as in Section A. When the peak amplifier 44 starts to operate, the efficiency is lowered once. However, the efficiency reaches the peak again at the compression point at which the peak amplifier 44 also starts to be saturated. The output from the carrier amplifier 42 and the output from the peak amplifier 44 are equal at the compression point.
In general, the CDMA signals and the multi-carrier signals have a high peak factor, that is, a ratio between peak power and average power is high. However, the general amplifiers employ an operating point which is lowered from the compression point correspondingly so as to be able to cope with a peak factor of 7 to 12 dB.
Referring now to FIG. 8, an example of impedances at the respective components will be described.
Since the value Z0, which is the output load 47, is specified to a constant value, this is employed as a starting point. An impedance Z7 of the node 58 with respect to the λ/4 transformer 46 is expressed as in a formula (1).[Expression 1]Z7=(Z2)2/Z0  (1)where Z2 is a characteristic impedance of the λ/4 transformer 46.
An impedance Z4 of the output matching circuit 53 of the carrier amplifier 42 with respect to the λ/4 transformer 57 is obtained in the same manner as shown above since an output impedance of the output matching circuit 56 of the peak amplifier 44 is substantially infinity in Section A. Since the load is equally divided in Section C, a load impedance of the amplifying circuit of the carrier amplifier 42 (an amount of contribution of the amplifying circuit at the node 58) and a load impedance of the output matching circuit 56 of the peak amplifier 44 are 2(Z7), respectively. Therefore, a formula (2) and a formula (3) are established.
A value Z5 here is the load impedance of the output matching circuit 56 of the peak amplifier 44 with respect to the peak amplifier 44 of the node 58, and Z1 is a characteristic impedance of the λ/4 transformer 57.
In Section B, the impedance Z4 and the impedance Z5 transfer between a value in Section A and a value in Section C.
In particular, changing of the load of the carrier amplifier 42 is referred to as a load modulation.
                    [                  Expression          ⁢                                          ⁢          2                ]                                                            (                  Section          ⁢                                          ⁢          A                )                                                                      Z          ⁢                                          ⁢          4                =                                                            (                                  Z                  ⁢                                                                          ⁢                  1                                )                            2                        Z7                    =                                                                      (                                      Z                    ⁢                                                                                  ⁢                    1                                    )                                2                                            (                                                                            (                                              Z                        ⁢                                                                                                  ⁢                        2                                            )                                        2                                    ⁢                                      /                                    ⁢                  Z                  ⁢                                                                          ⁢                  0                                )                                      =                          Z              ⁢                                                          ⁢              0              ⁢                                                                    (                                          Z                      ⁢                                                                                          ⁢                      1                                        )                                    2                                                                      (                                          Z                      ⁢                                                                                          ⁢                      2                                        )                                    2                                                                                                                        (                  Section          ⁢                                          ⁢          C                )                                                                      Z          ⁢                                          ⁢          4                =                                                            (                                  Z                  ⁢                                                                          ⁢                  1                                )                            2                                      2              ⁢                              (                                  Z                  ⁢                                                                          ⁢                  7                                )                                              =                                    (                              1                ⁢                                  /                                ⁢                2                            )                        ⁢            Z            ⁢                                                  ⁢            0            ⁢                                                            (                                      Z                    ⁢                                                                                  ⁢                    1                                    )                                2                                                              (                                      Z                    ⁢                                                                                  ⁢                    2                                    )                                2                                                                        (        2        )                                [                  Expression          ⁢                                          ⁢          3                ]                                                            (                  Section          ⁢                                          ⁢          A                )                                                                      Z          ⁢                                          ⁢          5                =        ∞                                                            (                  Section          ⁢                                          ⁢          C                )                                                                      Z          ⁢                                          ⁢          5                =                  2          ⁢                      (                          Z              ⁢                                                          ⁢              7                        )                                              (        3        )            
A case in which the Doherty amplifier is applied to a high-frequency area will be described.
That is, when the input signal level is high (Section C), the impedance Z4 is half the impedance value demonstrated when the input signal level is low (Section A). In other words, the impedance Z4 changes double in load. For example, when Z7=25Ω (ohm) and Z1=50Ω, the value of Z4 varies in a range between 100 and 50Ω. Therefore, the load impedance of the amplifying element 52 of the carrier amplifier 42 also varies.
In addition to the Doherty amplifier as described above, a Doherty amplifier which compensates deterioration of the characteristic by controlling gate bias voltage according to drain current especially for the carrier amplifier is known (for example, see Patent Document 1).
Patent Document 1: JP-A-2004-260232